Siemens, NVIDIA hit chip verification milestone for AI

Siemens and NVIDIA said they had reached a chip verification milestone using Siemens' Veloce proFPGA CS system, capturing tens of trillions of pre-silicon design cycles in a matter of days.

The announcement focuses on hardware-assisted verification for artificial intelligence and machine learning system-on-chip designs, where engineers must test large workloads before chips are manufactured. Siemens' FPGA-based prototyping platform was combined with NVIDIA's chip architecture to run verification at a scale that has been difficult to achieve with more established methods.

Verification is a critical stage in semiconductor development because it is intended to find flaws before first silicon is produced. Errors discovered after fabrication can lead to delays, redesigns, and higher costs, particularly in advanced AI chips, where both hardware and software stacks are complex.

Traditional tools such as simulation and emulation typically handle millions of cycles, or in some cases a few billion, within practical time limits. Siemens argued that current AI and machine learning designs require far larger test runs to meet reliability targets and product schedules.

FPGA-based prototype systems have long been used to execute pre-silicon workloads more quickly than software simulation. In this case, the Veloce proFPGA CS platform allowed NVIDIA's teams to run and capture much larger workloads before manufacturing, giving engineers a broader view of system behaviour under realistic conditions.

Verification Scale

The result is part of a broader collaboration on hardware-assisted verification methods, with a particular focus on FPGA-based prototyping. The system is intended to support both single-FPGA IP validation and larger chiplet-based designs involving billions of gates.

Jean-Marie Brunet, Senior Vice President and General Manager, Hardware Assisted Verification, Siemens Digital Industries Software, outlined the scope of that effort.

"NVIDIA and Siemens are partnering in many areas, most recently in advancing hardware-assisted verification methodologies in general and FPGA-based prototyping in particular, to adapt to the verification and validation demands presented by highly complex AI/ML SoCs," said Brunet.

"Veloce proFPGA CS is addressing these challenges by combining a highly flexible and scalable hardware architecture with an advanced, easy-to-use implementation and debug software flow, enabling customers to always have the optimal solution for single-FPGA IP validation as well as for multi-billion gate chiplet designs," Brunet said.

NVIDIA said the growing complexity of AI and computing architectures is increasing pressure on semiconductor teams to validate ever-larger workloads before launch. It linked the Siemens platform to its need for verification systems that can cope with that expansion in scale.

Narendra Konda, Vice President of Hardware Engineering, NVIDIA, said verification has become a constraint as AI processors grow in size and sophistication.

"As AI and computing architectures grow increasingly complex, semiconductor teams require high-performance verification solutions to validate massive workloads and accelerate time to market," said Konda.

"The integration of NVIDIA performance-optimized chip architectures with Siemens' Veloce proFPGA CS enables designers to capture trillions of cycles in days, providing the scale needed to ensure reliability for the next generation of AI," Konda said.

Industry Pressure

The development reflects broader pressure across the chip industry to shorten design cycles while handling larger, more software-dependent devices. AI processors are placing additional demands on verification because developers must test not only hardware logic, but also the interaction between silicon, firmware, and software workloads before production begins.

The challenge has become more acute as chipmakers adopt chiplet strategies and push to larger designs, making exhaustive testing harder to complete within commercial timelines. Running longer pre-silicon workloads can help expose bugs that would not appear in shorter tests.

For Siemens, the announcement highlights an area where electronic design automation suppliers are trying to differentiate themselves as AI-related semiconductor spending rises. For NVIDIA, it points to the growing importance of verification infrastructure in bringing advanced AI chips to market with fewer risks tied to first silicon.